As the integrated circuit (IC) fabrication moves to advanced technology nodes, the IC feature size scales down to smaller dimensions. For example, the trench dimensions and gate sizes continue to get smaller and smaller. One limitation to achieving smaller sizes of IC device features is conventional lithography. Small trench formation typically requires a high cost exposure tool, such as extreme ultraviolet (EUV) lithography tools that are constrained by scanner wavelength and various patterns for blocking certain wavelengths. A large etching bias is generally required to compensate for the large lithographic pattern for non-shrinkable critical dimensions, which often results in poor critical dimension uniformity or shorting of the gate when blocking patterns are misaligned. Thus, better methods and materials are needed to define small trench dimensions.